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RT9991 1 ds9991-01 april 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations (top view) vqfn-32l 5x5 power management ic for ssd general description the RT9991 is a 3-ch pmic for ssd (solid-state drive). it integrates 3 synchronous buck converters and one voltage detector. the RT9991 provides 3 independent enable pins for sequence control and auto discharge when powered off on the power line of a nand flash. the frequency can be up to 1.5mhz for buck 1and buck 2, and up to 2mhz for buck 3, hence allowing the use of smaller sized inductors to meet the space and height limit in handheld applications. to maximize power utilization, the RT9991 is designed with extremely low quiescent current. the buck converter can consume down to 70 a when operating in standby mode. the RT9991 is available in a vqfn-32l 5x5 package. features z z z z z supply input voltage range : 2.8v to 5.5v z z z z z buck 1 / buck 2 ` ` ` ` ` adjustable output voltage for v core or dram cache ` ` ` ` ` output current up to 1a ` ` ` ` ` switching frequency : 1.5mhz z z z z z buck 3 ` ` ` ` ` adjustable output version for nand flash ` ` ` ` ` output current up to 3a ` ` ` ` ` switching frequency : 2mhz ` ` ` ` ` auto discharge function z z z z z voltage detector ` ` ` ` ` programmable threshold voltage ` ` ` ` ` open-drain reset output z z z z z rohs compliant and halogen free applications z 1.8/2.5 inch solid-state drives z portable devices z usb-based hand-held products marking information gnd lx3 lx3 lx3 lx2 vin2 gnd gnd reset vdet nc fb1 nc nc nc fb2 vin3 vin3 gnd vin1 nc gnd en1 en2 en3 gnd vin1 vin2 lx1 lx2 fb3 lx1 33 gnd 24 23 22 21 1 2 3 4 10 11 12 13 31 30 29 28 20 19 5 6 9 32 14 27 18 7 15 26 16 25 17 8 RT9991 gqv ymdnn RT9991gqv : product number ymdnn : date code RT9991 package type qv : vqfn-32l 5x5 (v-type) lead plating system g : green (halogen free and pb free)
RT9991 2 ds9991-01 april 2011 www.richtek.com function block diagram typical application circuit buck converter 1 lx1 vin1 buck converter 2 lx2 vin2 buck converter 3 lx3 vin3 fb1 fb2 fb3 reset 0.7v gnd vdet en1 en2 en3 + - RT9991 lx1 v out1 1.2v/1a 16, 17 r1 r2 l1 2.2h 10f 30k 64.9k c2 fb1 13 vin1 v in 15, 20 c1 gnd 1, 18, 19, 22, 23, 32, 33 (exposed pad) lx2 v out2 1.8v/1a 24, 25 r3 r4 l2 2.2h 10f 80k 64.9k c3 fb2 28 lx3 v out3 3.3v/3a 2, 3, 4 r5 r6 l3 1h 10f x 2 200k 64.9k c4 fb3 8 vin2 21, 26 vin3 5, 6 5v vdet 11 reset 10 v dd 3.3v 43k r7 r8 r9 en1 14 en2 27 en3 7 chip enable
RT9991 3 ds9991-01 april 2011 www.richtek.com pin no. pin name pin function 1, 18, 19, 22, 23, 32, 33 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 2, 3, 4 lx3 buck converter 3 switch output (inductor connection point). 5, 6 vin3 buck converter 3 power supply input. 7 en3 buck converter 3 chip enable (active high). 8 fb3 buck converter 3 feedback input. 9, 12, 29, 30, 31 nc no internal connection. 10 reset reset output. 11 vdet threshold voltage detect setting. 13 fb1 buck converter 1 feedback input. 14 en1 buck converter 1 chip enable (active high). 15, 20 vin1 buck converter 1 power supply input. 16, 17 lx1 buck converter 1 switch output (inductor connection point). 21, 26 vin2 buck converter 2 power supply input. 24, 25 lx2 buck converter 2 switch output (inductor connection point). 27 en2 buck converter 2 chip enable (active high). 28 fb2 buck converter 2 feedback input. functional pin description
RT9991 4 ds9991-01 april 2011 www.richtek.com parameter symbol test conditions min typ max unit buck converter 1 quiescent current i q no load, no switching -- 70 -- a shutdown current i shdn en = gnd -- 0.2 -- a feedback reference voltage v fb -- 0.8 -- v v in rising -- 2.1 -- uvlo under voltage lockout threshold v uvlo hysteresis -- 0.1 -- v logic-high v ih 1.5 -- v in v en1 threshold voltage logic-low v il -- -- 0.4 v peak current limit i lim 1.3 1.7 -- a oscillator frequency f os c v in = 3.6v, i out = 300ma 1.2 1.5 1.8 mhz st a r t -up tim e i ou t = 0ma. time from active en to 90% of v out -- 250 -- s p-mosfet on resistance r ds(on)_p v in = v gs = 3.6v, pwm mode -- 250 -- m n-mosfet on resistance r ds(on)_n v in = v gs = 3.6v, pwm mode -- 260 -- m buck converter 2 quiescent current i q no load, no switching -- 70 -- a shutdown current i shdn en = gnd -- 0.2 -- a feedback reference voltage v fb -- 0.8 -- v (v in = 5v, t a = 25 c, unless otherwise specified) electrical characteristics recommended operating conditions (note 4) z supply input voltage , v in ----------------------------------------------------------------------------------------- 2.8v to 5.5v z junction temperature range ------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply input voltage, v in ----------------------------------------------------------------------------------------- ? 0.3v to 6.5v z lx pin v oltage ------------------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) z other pins voltage ------------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z power dissipation, p d @ t a = 25 c vqf n-32l 5x5 ------------------------------------------------------------------------------------------------------ 2.778w z package thermal resistance (note 2) vqfn-32l 5x5, ja ------------------------------------------------------------------------------------------------- 36 c/w vqfn-32l 5x5, jc ------------------------------------------------------------------------------------------------ 6 c/w z lead temperature (soldering, 10 sec.) ----------------------------- ------------------------------------------- 260 c z junction temperature ---------------------------------------------------------------------------------------------- 150 c z storage temperature range ------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) --------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ----------------------------------------------------------------------------------------------- 200v to be continued
RT9991 5 ds9991-01 april 2011 www.richtek.com parameter symbol test conditions min typ max unit v in rising -- 2.1 -- uvlo under voltage lockout threshold v uvlo hysteresis -- 0.1 -- v logic-high v ih 1.5 -- v in en2 threshold voltage logic-low v il -- -- 0.4 v peak current limit i lim 1.3 1.7 -- a oscillator frequency f osc v in = 3.6v, i out = 300ma 1.2 1.5 1.8 mhz start-up time i ou t = 0ma time from active en to 90% of v out -- 250 -- s p-mosfet on resistance r ds(on)_p v in = v gs = 3.6v, pwm mode -- 250 -- m n-mosfet on resistance r ds(on)_n v in = v gs = 3.6v, pwm mode -- 260 -- m buck converter 3 quiescent current i q no load, no switching -- 80 -- a shutdown current i shdn en = gnd -- 0.2 -- a feedback reference voltage v fb 0.8 -- v v in rising -- 2.4 -- uvlo under voltage lockout threshold v uvlo hysteresis -- 0.1 -- v logic-high v ih 1.5 -- v in en3 threshold voltage logic-low v il -- -- 0.4 v peak current limit i lim 3.5 3.9 -- a oscillator frequency f osc v in = 3.6v, i out = 300ma 1.6 2 2.4 mhz start-up time no load. time from active en to 90% of v out 2000 -- -- s p-mosfet on resistance r ds(on)_p v in = v gs = 3.6v, pwm mode -- 110 -- m n-mosfet on resistance r ds(on)_n v in = v gs = 3.6v, pwm mode -- 110 -- m voltage detector v in rising (l to h) 0.693 0.7 0.707 voltage detection threshold v in falling (h to l) 0.673 0.68 0.687 v v delay (l to h) 70 100 130 ms voltage detection delay time v delay (h to l) 5 10 20 s thermal protections thermal shutdown threshold t sd -- 160 -- c thermal shutdown hysteresis t sd -- 25 -- c
RT9991 6 ds9991-01 april 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high-effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT9991 7 ds9991-01 april 2011 www.richtek.com buck1 output accuracy vs. load current -0.6% -0.4% -0.2% 0.0% 0.2% 0.4% 0.6% 0.001 0.01 0.1 1 load current (a) output voltage accuracy (% ) typical operating characteristics buck1 efficiency vs. load current 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 load current (a) efficiency (%) v buck1 = 1.2v v in1 = 2.8v v in1 = 3.6v v in1 = 4.2v v buck1 = 1.2v, v in1 = 5v 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 0.001 buck2 output accuracy vs. load current -0.6% -0.4% -0.2% 0.0% 0.2% 0.4% 0.6% 0.001 0.01 0.1 1 load current (v) output voltage accuracy (% ) v buck2 = 1.8v, v in2 = 5v 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 0.001 buck3 output accuracy vs. load current -0.6% -0.4% -0.2% 0.0% 0.2% 0.4% 0.6% 0.001 0.01 0.1 1 10 load current (a) output voltage accuracy (% ) v buck3 = 3.3v, v in3 = 5v 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 0.001 buck2 efficiency vs. load current 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 load current (a) efficiency (%) v buck2 = 1.8v v in2 = 2.8v v in2 = 3.6v v in2 = 4.2v buck 3 efficiency vs. load current 30 40 50 60 70 80 90 100 110 0.01 0.1 1 10 load current (a) efficiency (%) v in3 = 3.6v v in3 = 4.2v v in3 = 5v v buck3 = 3.3v
RT9991 8 ds9991-01 april 2011 www.richtek.com buck2 output ripple time (500ns/div) v in2 = 5v, i load = 1a v out2 (20mv/div) i lx2 (1a/div) v lx2 (5v/div) v in3 = 5v, i load = 1a v out3 (20mv/div) i lx3 (1a/div) v lx3 (5v/div) buck3 output ripple time (250ns/div) buck1 load transient response time (50 s/div) i load = 40ma to 0.7a v buck1 (100mv/div) i out (200ma/div) buck2 load transient response time (50 s/div) v buck2 (100mv/div) i out (200ma/div) i load = 40ma to 0.7a buck1 output ripple time (500ns/div) v in1 = 5v, i load = 1a v out1 (20mv/div) i lx1 (1a/div) v lx1 (5v/div) buck3 load transient response time (50 s/div) i load = 40ma to 2.5a v buck3 (200mv/div) i ldo (1a/div)
RT9991 9 ds9991-01 april 2011 www.richtek.com application information the basic RT9991 application circuit is shown in the section typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in and decreases with higher inductance, as shown in equation below : where f is the operating frequency and l is the inductance. having a lower ripple current reduces not only the esr losses in the output capacitors, but also the output voltage ripple. higher operating frequency combined with smaller ripple current is necessary to achieve high efficiency. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4i (max) . the largest ripple current occurs at the highest vin. to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the high side mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : this formula has a maximum at v in = 2v out , where i rms = i out(max) / 2. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : the output ripple is the highest at the maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr, but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density, but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistakened as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. output voltage programming the resistive divider allows the fb pin to sense a fraction of the output voltage as shown below out out l in vv i1 fl v ?? ?? = ? ?? ?? ?? ?? out out l(max) in(max) vv l1 fi v ??? ? =? ??? ? ??? ? ??? ? out in rms out(max) in out v v ii 1 vv =? out l out 1 viesr 8fc ?? ??? + ?? ??
RT9991 10 ds9991-01 april 2011 www.richtek.com lx r1 r2 v out fb gnd RT9991 where v fb is the internal reference voltage 0.8v (typ.). checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing which would indicate a stability problem. chip enable operation if the en pin for the selected buck is pulled high and the input voltage is greater than the under voltage lockout threshold, the selected buck will be turned on. buck1 can be turned on/off by the external en1 pin; buck2 can be turned on/off by the external en2 pin; buck3 can be turned on/off by the external en3 pin. for adjustable voltage mode, the output voltage is set by an external resistive divider according to the following equation : output buck 1 buck 2 buck 3 state on on on en vin1 > en1 > 1.5v vin1 > en2 > 1.5v vin1 > en3 > 1.5v uvlo 5.5v > vin1 > 2.1v 5.5v > vin2 > 2.1v 5.5v > vin3 > 2.4v default output voltage ou t fb r1 v v1 r2 ?? =+ ?? ?? v fb = 0.8v table 1. the RT9991 power terminology voltage detector reset is an open drain output that indicates whether the vdet voltage is higher than 0.7v or not. reset is typically pulled up to 3.3v. vdet monitors the input voltage and triggers the reset output (figure 1). reset is high impedance when the voltage from vdet exceeds the rising threshold 0.7v (typ.). reset is low when the voltage from vdet falls below the low-battery falling threshold 0.68v (typ.) (figure 2). if the voltage detector feature is not required, connect reset to ground and connect vdet to vin. + - 3.3v reset 0.7v vdet figure 1. vdet and reset circuit figure 2. vdet and reset comparator waveform out fb r1 v v1 r2 ?? =+ ?? ?? 0.68v 0.7v vdet reset delay choosing the inductor the RT9991 includes a current-reversal comparator which monitors inductor current and disables the synchronous rectifier as current approaches zero. this comparator will minimize the effect of current reversal for higher efficiency. for some low inductance values, however, the inductor current may still reverse slightly. this value depends on the speed of the comparator in relation to the slope of the current waveform, given by v l / l. v l is the voltage across the inductor (approximately ? v out ) and l is the inductance value. an inductance value of 2.2 h is a good starting value. as the inductance is reduced from this value, the RT9991 will enter discontinuous conduction mode at progressively
RT9991 11 ds9991-01 april 2011 www.richtek.com higher loads. ripple at v out will increase directly proportionally to the magnitude of inductor ripple. transient response, however, will improve. a smaller inductor changes its current more quickly for a given voltage drive than a larger inductor, resulting in faster transient response. a larger inductor will reduce output ripple and current ripple, but at the expense of reduced transient performance and a physically larger inductor package size. for this reason a larger c vout will be required for larger inductor sizes. the input regulator has an instantaneous peak current clamp to prevent the inductor from saturating during transient load or start-up conditions. the clamp is designed so that it does not interfere with normal operation at high loads and reasonable inductor ripple. it is intended to prevent inductor current runaway in case of a shorted output. the dc winding resistance and ac core losses of the inductor will also affect efficiency, and therefore available output power. these effects are difficult to characterize and vary by application. some inductors and capacitors that may be suitable for this application are listed in table below : length (mm) width (mm) height (mm) inductance ( h) rdc (m ) idc (a) p/n max. max. max. l max. max. supplier vlf5012st-1r0n2r5 5 4.8 1.2 1 50 3.3 vlf5014st-2r2m2r3 5 4.8 1.4 2.2 73 3 vlf3010a-1 3 2.8 1 2.2 120 1 vlf3012a 3 2.8 1.2 2.2 100 1 vls2010e 2.1 2.1 1 2.2 228 1 vls2012e 2.1 2.1 1.2 2.2 153 1 td k nr6045t1r0n 6 6 4.5 1 19 4.2 cb2016t2r2m 2.2 1.8 1.8 2.2 130 1 nr6020t2r2n 6 6 2 2.2 34 2.7 nr3015 3 3 1.5 2.2 60 1.48 taiyo lps4018 3.9 3.9 1.7 3.3 80 2.2 coilcraft d53lc 5 5 3 3.3 34 2.26 db318c 3.8 3.8 1.8 3.3 70 1.55 to k o we-tpc type m1 4.8 4.8 1.8 3.3 65 1.95 wurth table 2
RT9991 12 ds9991-01 april 2011 www.richtek.com layout considerations follow the pcb layout guidelines for optimal performance of RT9991. ` place the input capacitor as close as possible to the device pins (vin and gnd). ` lx node is with high frequency voltage swing and should be kept in a small area. ` connect feedback network behind the output capacitors. ` keep the switching area small. place the feedback components near the RT9991. ` connect all analog grounds to a common node and then connect the common node to the power ground behind the output capacitors. figure 3. derating curve for the RT9991 package 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT9991, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for vqfn- 32l 5x5 packages, the thermal resistance, ja , is 36 c/ w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (36 c/w) = 2.778w for vqfn-32l 5x5 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT9991 package, the derating curve in figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
RT9991 13 ds9991-01 april 2011 www.richtek.com figure 4. pcb layout guide v out1 gnd lx3 lx3 lx3 lx2 vin2 gnd gnd reset vdet nc fb1 nc nc nc fb2 vin3 vin3 gnd vin1 nc gnd en1 en2 en3 gnd vin1 vin2 lx1 lx2 fb3 lx1 33 gnd 24 23 22 21 1 2 3 4 10 11 12 13 31 30 29 28 20 19 5 6 9 32 14 27 18 7 15 26 16 25 17 8 v out2 v out3 v in the feedback resistor divider must be placed as close to t he fb pin as possible. the output capacitor must be close to the ic. the lx pin should be connected to the inductor by a wide and short trace, keep sensitive components away from this trace. place c in between vin and gnd and it should be as close as possible to the ic.
richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. RT9991 14 ds9991-01 april 2011 www.richtek.com richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension e d 1 d2 e2 l b e a a1 a3 see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 4.950 5.050 0.195 0.199 d2 3.400 3.750 0.134 0.148 e 4.950 5.050 0.195 0.199 e2 3.400 3.750 0.134 0.148 e 0.500 0.020 l 0.350 0.450 0.014 0.018 v-type 32l qfn 5x5 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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